1. Field of the Invention
The present invention relates to a semiconductor device preferable for realizing a large-scale function system on a single chip and in particular, to a semiconductor device having terminals of an identical function at a plurality of sides of a macro cell, so that these terminals can selectively be used.
2. Description of the Related Art
It is known to combine logic properties whose operations have been verified, so as to constitute a functional system on a single chip. For example, by arranging (layout) macro cells such as an MPU and a DSP and various macro cells such as a memory and various I/O interfaces on a chip and connecting the macro cells by wiring, it is possible to realize a so-called system LSI having various functions dedicated to a particular use.
FIG. 15 shows a configuration of a macro cell designed for a single chip and used as a single chip. In FIG. 15, a reference symbol 100 denotes a chip (single chip), 101 to 164 denote pads (external electrodes), and 200 denotes a macro cell formed on the chip. The pads 101 to 104 are located at positions considering the pin arrangement of a package (containing a semiconductor chip) (not depicted). Here is given an example in which a first output pad 101 is arranged at the left side of the chip 100, a second output pad 102 is arranged at the lower side a third output pad 103 is arranged at the right side, and an input pad 104 is arranged at the upper side.
The macro cell 200 includes: an internal kernel circuit block 300 performing a predetermined functional operations; three output buffers 210, 220, and 230; an input buffer 240; three output terminals 201, 202, and 203; and an input terminal 204. The internal kernel circuit block 300 has a circuit portion (not depicted) performing a predetermined functional operation according to an input signal and terminals 301 to 304.
The terminals 201 to 204 for connecting the macro cells are designed considering the arrangement of the pads 101 to 104. The input terminal 204 is arranged at the upper side of the macro cell 200 and the output terminals 201, 202, and 203 are arranged at.the left side, the lower side, and the right side, respectively. The pads 101 to 104 are connected to the terminals 201 to 204 of the macro cell 200 by the macro external wires 111 to 114. The terminal arrangement of the internal kernel circuit block 300 is designed considering the arrangement of the terminals (for connecting the macro cells) of the macro cell 200. An input terminal 304 is arranged at the upper side of the internal kernel circuit block 300, and a first, a second, and a third output terminal 301, 302, and 303 are arranged at the left side, at the lower side, and at the right side of the internal kernel circuit block 300.
An input buffer 240 is arranged between the input terminal 204 of the macro cell 200 and the input terminal 304 of the internal kernel circuit block 300, and the input terminal 204 of the macro cell 200 is connected to the input terminal of the input buffer 240 by an in-macro wire while the output terminal of the input buffer 240 is connected to the input terminal 304 of the internal kernel circuit block 300 by an in-macro wire. A first output buffer 210 is arranged between the first output terminal 301 of the internal kernel circuit block 300 and the first output terminal 201 of the macro cell 200, and the first output terminal 301 of the internal kernel circuit block 300 is connected to the input terminal of the first output buffer 210 by an in-macro wire while the output terminal of the first output buffer 210 is connected to the first output terminal 201 of the macro cell 200 by an in-macro wire. Similarly, via the second and the third output buffers 220 and 230, the output terminals 302 and 303 of the internal kernel circuit block 300 are connected to the output terminals 202 and 203 of the macro cell.
In FIG. 15, the respective terminals are located so as to minimize the wires outside and inside the macro cell. This reduces a signal transfer delay caused by wiring, thereby enabling to obtain a high-speed operation.
FIG. 16 shows a combination of a macro chip designed for a single chip and a macro chip designed for a logic core. FIG. 16 shows.a configuration example having the macro cell 200 (designed for a single chip) shown in FIG. 15 arranged together with another macro cell (designed for the IP) located below the macro cell 200. The macro cell 400 includes input terminals W, X, and Y via which output signals of the macro cell 200 are fed, and an output terminal Z for outputting a signal (input signal to the macro cell 200) supplied to the macro 200. Here, the terminals W, X, Y and Z are arranged at the upper side of the macro cell 400.
When the macro cell 200 designed as a single chip is used as it is in combination with the macro cell 400 for the logic arranged below the macro cell 200, a macro-connecting wire 501 between the first output terminal 201 and the first input terminal W needs to be quite long. When the wire becomes longer, the wire capacity is increased, causing a delay in signal transfer. To cope with this, a buffer 510 is arranged in the route of the macro-connecting wire 501, so as to reduce the signal transfer delay. A macro-connecting wire 502 between the second output terminal 201 and the second input terminal X is short, and they are connected to each other directly without providing a buffer. A macro-connecting wire 503 between the third output terminal 203 and the second input terminal Y is long, and they are connected to each other via a buffer. A macro-connecting wire 504 between the output terminal Z and the input terminal 204 is further longer, and they are connected to each other via two buffers arranged at a certain interval.
FIG. 17 shows a configuration example of using a macro cell designed for the logic core in combination with another macro cell designed for the logic core. The macro cell 600 shown in FIG. 17 is identical to the internal kernel circuit block 300 shown in FIG. 15 and FIG. 16 and has a functional operation identical to that of the macro cell 200 shown in FIG. 15 and FIG. 16. In this macro cell 600, the terminals W, X, Y, and Z are arranged at the lower side considering a connection with the other macro cell 400 arranged below. Since locations of the terminals W, X, Y, and Z are changed, the location of the input buffer 240 and the in-macro wiring are different from the macro cell 200 shown in FIG. 15 and FIG. 16. By using the macro cell 600 having such a terminal arrangement, it is possible to reduce the macro-connecting wires 511 to 514.
FIG. 18 shows a configuration example for realizing a single chip by using a macro cell designed for the logic core. When utilizing the macro cell (designed for the logic core) 600 shown in FIG. 17 to constitute a chip having the pad arrangement shown in FIG. 15, it is necessary to use long wires between the terminals w, y, z arranged at the lower side of the macro cell 600 and the pads 101, 103, and 104. To cope with this, an output buffer 710 is arranged in the wire between the terminal w and the pad 101, and an output buffer 720 is arranged in the wire between the terminal y and the pad 103. Furthermore, in the wire between the pad 104 and the terminal z, there are arranged input buffers 730 and 740 at a certain interval. This reduces the delay in signal transfer caused by increase of the wire capacity.
Japanese Patent Publication 6-140566 discloses a semiconductor integrated circuit having a plurality of mega macro cells having terminals connected to one another by macro external wires, wherein identical terminals are arranged at the four sides of the mega macro cell and are electrically connected to one another, thereby improving the wiring efficiency. Since identical terminals are arranged at the four sides of the mega macro cell, it is possible to connect mega macro cells by connecting terminals of the opposing sides of the adjacent macro cells.
As shown in FIG. 16, when connecting a macro cell designed for a single chip (having terminals distributed to the respective sides) to another macro cell, the wire between the macro cells may be quite long, which increases the signal transfer delay time. Although it is possible to suppress the signal transfer delay by providing a buffer in the wire route, the signal transfer is delayed according to the wire length.
As shown in FIG. 18, when utilizing a macro cell designed for the logic core (having terminals arranged at particular sides) to constitute a single chip, a long wire is required between the macro terminals and the external terminals (pads) of the chip, causing a problem of the signal delay.
As shown in FIG. 17, by arranging macro cells in such a manner that sides having terminals oppose to each other, it is possible to reduce the length of the macro-connecting wire. However, it is often difficult to arrange a plenty of macro cells in this way.
When identical terminals are arranged at the respective sides of a macro cell, it is possible to increase the flexibility of the macro cell layout (floor plan). However, when the terminals arranged at the respective sides are connected to one another, the total wire length is increased, which in turn increases the signal transfer delay time.
It is therefore an object of the present invention to provide a semiconductor device capable of increasing the flexibility of the macro cell layout (floor plan) and reducing the delay caused by wires. Another object of the present invention is to provide a semiconductor device which can be used both for the single chip and the logic core. Still another object of the present invention is to provide a semiconductor device in which terminals having an identical function and arranged at a plurality of sides of the macro cell can be selectively used by an external signal.
In order to achieve the aforementioned object, the semiconductor device according to the present invention includes terminals having an identical function at least at two sides of a macro cell and a terminal selector for selecting at least one of the terminals having the identical function.
Since terminals having an identical function are arranged at the respective sides of a macro cell, it is possible to obtain a high degree of freedom in the macro arrangement designing (floor plan). By using terminals in the vicinity of the connection destination, it is possible to reduce the macro-connecting wire. Since the terminal selector is provided, it is possible to make a connection to the kernel circuit in the macro cell by using only the terminal to be used. Moreover, since the terminal selector is provided, it is possible to isolate the wires to the respective terminals from one another. This enables to reduce the signal delay by wiring and obtain a high-speed operation. It should be noted that by selecting a terminal to be used, this can be used for both as a macro cell for a single chip and as a macro cell for a logic core.
When the terminals having an identical function are input terminals, the terminal selector is composed of an AND circuit and an OR circuit. When the AND circuit is used, the input terminals not to be used are fixed to logical 1. When the OR circuit is used, the input terminals not to be used are fixed to logical 0. Thus, the signal of the input terminal to be used is supplied via the AND circuit to the input terminal of the kernel circuit. It should be noted that when the AND circuit is used, its input terminals are pulled up and when the OR circuit is used, its input terminals are pulled down. When pull up or pull down is performed, wiring is performed only to the input terminal to be used.
When the terminals having an identical function are output terminals, a buffer circuit is provided for each of the output terminals. Thus, it is possible to isolate the wires to the respective output terminals from one another, thereby enabling to reduce the signal delay by wiring and obtain a high-speed operation. Since the same signals output to the plurality of output terminals having an identical function, wiring is required only for the output terminal to be used. It should be noted that by connecting a plurality of output terminals in parallel to one another, it is possible to increase the output drive capability. It should be noted that it is also possible to provide a tri-state buffer circuit for each of the output terminals. When the tri-state buffer circuit is used, it is possible to control the output terminals not to be used, in a non-output state (high impedance). This can reduce the power for driving the wire to the output terminal not to be used.
According to another aspect of the present invention, the semiconductor device includes terminals having an identical function at least at two sides of a macro cell and a terminal changer for changing at least one of the terminals having the identical function according to a terminal specifying data.
Since terminals having an identical function are arranged at the respective sides of the macro cell, it is possible to obtain a high degree of freedom in macro arrangement designing (floor plan). By using a terminal in the vicinity of the terminal as the connection destination, it is possible to reduce the macro-connecting wire. Since the terminal changer is provided, it is possible to change the terminal to be used after the wire connection. Accordingly, after manufacturing a semiconductor device having a plurality of wire routes of the same signal, it is possible to select an optimal wire route. Moreover, it is possible to supply a test signal to a particular terminal and select that terminal, thereby performing a macro operation test.
It should be noted that the terminal specifying data is a parae data, which is latched by a data latch circuit provided in the macro cell, so that an input terminal and an output terminal are selected according to the output of the latch. Moreover, it is also possible to supply the terminal specifying data as a serial data to the shift register provided in the macro cell, so that an input terminal and an output terminal are selected according to the output of the shift register. By supplying the terminal specifying data, it is possible to specify an input terminal and an output terminal to be used. When the terminal specifying data is a serial data, it is possible to reduce the number of terminals for supplying the terminal specifying data. Furthermore, by supplying the output of the final stage of the shift register to the serial data input terminal of another macro cell, it is possible to select/specify a terminal to be used for the other macro cell.